An Efficient Design Methodology for CNFET Based Ternary Logic Circuits

Abstract

Ternary logic is a promising alternative to conventional binary logic. Implementation of ternary logic circuits however requires devices with multiple thresholds, which is a complex task with current CMOS technology. Carbon Nanotube based FETs (CNFETs) present an easier alternative for the implementation of ternary logic circuits since their threshold voltages can be varied by varying the diameter. In existing design methodology of ternary logic circuits, ternary signals are first converted to binary signals using ternary decoders which are then passed through binary gates and an encoder to get the final ternary output. Since every input signal requires a ternary decoder, the resulting circuits lead to increased area, power and delay. In this paper, authors suggest a new transistor-level methodology for designing CNFET-based ternary circuits without using ternary decoders. Elimination of decoders results in reduced area, power and delay. Simulation results indicate that up to 88% reduction in power consumption, 64% reduction in transistor count and 12 % reduction in delay can be achieved using the proposed approach when compared to the existing one.