Abstract
In this paper we propose an efficient cluster refinement approach for macro-cell placement. The algorithm selects a cluster of blocks dynamically, and finds an optimal solution for all the blocks in the cluster simultaneously. This is different from previous zone refinement approach which optimizes the allocation of one single block in each operation. Experimental results on the MCNC benchmark circuits show that the approach achieves excellent area utilization while minimizing the wire length at the same time.
Highlights
Placement of blocks on a 2D surface is one critical process in VLSI layout design
Onodera et al [13] presents a building block placement approach which employs a branch-andbound strategy to search for an optimal solution within the whole solution space of size 2n(n+2>
We present a new cluster refinement approach, which consists of the following three parts: (1) sequential cluster selection which reduces the complexity of the problem to a manageable degree; (2) cluster optimization which employs an efficient branch-and-bound strategy to search for an optimal solution for all the blocks in the cluster; (3) adaptive cluster overlapping which explores larger solution space to achieve better results
Summary
Placement of blocks on a 2D surface is one critical process in VLSI layout design. The major objectives are chip area and wire length minimization. Onodera et al [13] presents a building block placement approach which employs a branch-andbound strategy to search for an optimal solution within the whole solution space of size 2n(n+2>. Large problems are decomposed to reduce the number of blocks below the manageable limit, and a placement is constructed hierarchically in a bottom-up manner. H. Murata et al [11] introduces a P-admissible solution space of size (n!)2 8n, where n is the total number of blocks, and applies a simulated annealing method to search for a good solution. We present a new cluster refinement approach, which consists of the following three parts:. Experimental results show that the algorithm obtains excellent area utilization while minimizing the wire length at the same time.
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