Abstract
Built-in-self-test (BIST) response data can be compacted using a linear-feedback shift register (LFSR). Prior work has indicated that the probability of aliasing tends to converge to 2-k for a polynomial of degree k and large test length, and that primitive polynomials perform better than non-primitive polynomials. Nearly all analytical models and simulations have been based on the assumption that error occurrences are statistically-independent. This paper presents the first statistical results, based on fault simulation, that show that this convergence property holds for actual digital logic circuits and randomly-generated test vector sequences. However, it is shown that the average probability of aliasing is unsuitable as a design metric, and that a 95% upper confidence limit (UCL) is more useful. This paper introduces a UCL for the loss of fault coverage due to test response compaction. The theoretical or “ideal” UCL is shown to match closely the empirically-derived UCL obtained by fault simulation. The result is that a tight lower bound on fault coverage for LFSR-based BIST configurations can be obtained easily. Fault coverage for a BIST configuration can be obtained without the LFSR, eliminating costly fault simulation of the full structure with the LFSR. These results have been incorporated in the standard procedure for fault coverage measurement.
Highlights
Built-in-self-test (BIST) response data can be compacted using a linear-feedback shift register (LFSR)
This paper reports the results of fault simulations involving a variety of CUTs based on actual circuits and the ISCAS ’85 cc;mbinational benchmark set
An upper confidence limit on the loss of fault coverage is derived, and it is shown that this value closely matches the empirically-derived values that result from the fault simulation experiments
Summary
Experiments were conducted to obtain statistics on aliasing. This section summarizes details of the MISR configuration, circuits, and test vector sequences for which the statistics were obtained. The outputs of the CUT are inputs to XOR gates between the flip-flop stages, and so the degree of the MISR must be greater than or equal to the number of primary outputs of the CUT. P2 is the first primitive polynomial of appropriate degree listed in Peterson and Weldon [2]. IR1 is the first irreducible but non-primitive polynomial of appropriate degree listed in Peterson and Weldon [2]. IR3 is the second primitive polynomial of appropriate degree listed in Peterson and Weldon [2], and IR4 is the third.
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