Elimination of the effect of bottom-plate capacitors in C-2C DAC using a layout technique

Abstract

An efficient layout technique is proposed to eliminate the effect of the bottom-plate capacitors in a C-2C Digital to Analog Converter (DAC). Using this technique, the bottom-plate capacitors of 2C capacitors in the C-2C structure are placed in parallel with 1C capacitors. Then, the effect of the bottom plate capacitors is nulled by modifying the size of the main 1C capacitors. Hence, avoiding the complexity of calibration, this technique can preclude the effect of the bottom-plate to ground capacitance. Statistical simulations prove that the proposed technique is robust to non-ideal effects such as mismatch or parasitic capacitors. A 10-bit C-2C DAC is modeled in COMSOL Multiphysics using the TSMC 90nm technology parameters to demonstrate the proposed method. Simulation results prove that the peak of INL and DNL are improved by factors of 66 and 116 compared to the conventional C-2C DAC. Moreover, using this technique multi-layer capacitors can be used along with MIM capacitors to increase the capacitance density. In a 90nm CMOS technology, the area of the capacitors in a 10-bit C-2C DAC is reduced by more than 63%.