Electronic technology and the SLD detector

Abstract

Abstract The SLD detector consists of five major subsystems, each with associated front-end electronics and an integrated FASTBUS control and data acquisition system. This paper highlights the choices among electronic technologies that have been developed for the SLD detector electronics. The common control, calibration, and data acquisition architectures are described. The functions of selected SLD integrated circuits, standard cells, gate arrays, and hybrids are summarized, and the integration of these functions into the common data acquisition path is described. Particular attention is directed to four areas of electronic technology developed for the SLD detector: (1) the preamplifier hybrid designs are compared and their performance and implementation examined; (2) the application of full custom CMOS digital circuits in SLD is compared to gate array and EPLD (electrically programmable logic device) implementations; (3) the fiber optic signal transmission techniques in SLD are examined and the data rates and link topology are presented; and (4) finally, the packaging, power consumption, and cooling requirements for system functions resident inside the detector structure are explored. The rationale for the implementation choices in the SLD electronics is presented so that others might benefit from our experience.