Data acquisition system for a KL experiment at J-Parc

Abstract

We present the proposed Data Acquisition (DAQ) system for KOTO, a KL→πνν experiment at J-Parc, Japan. It comprises two distinctive blocks: a 14(12)-bit, 125 (500) MHz ADC module for reading the approximately 4000 frontend channels; and a digital Trigger module able to provide a detector-wise synchronous energy sum. A Master Clock and Trigger Supervisor Module, with fans out of control signals to the whole system, completes the DAQ Architecture. The front-end readout board amplifies analog pulses from 16 photomultipliers and passes them through a 10-pole shaper before digitization. Data are then processed locally with field programmable gate arrays (FPGAs) to determine real-time energy values for the system Trigger Supervisor. The ADC module is provided with a pipeline, up to 4us long, which stores the acquisitions, awaiting the system trigger pulse. After a trigger, data are packed and buffered on on-board memories for readout via the VME32/64 backplane. The full design and preliminary test results will be described. I. SYSTEM ARCHITECTURE We present the Data Acquisition (DAQ) System for the Step-1 phase of the K0TO experiment [1], a high energy physics kaon experiment at the Japan Particle Accelerator Research Complex (J-PARC). The goal of the experiment is to measure the rate of the rare decay KL→πνν. This flavour changing neutral current decay is predicted by the Standard Model (SM) to happen only once every 3.3x1011 KL decays. If not observed or observed at a rate very different from the SM predictions, it will shed light on the mechanism responsible for CP in the quark sector. The DAQ Architecture comprises three functional blocks: front-end modules for the readout and digitization of the ~4000 channels in the K0TO detector; digital trigger modules with a dead timeless two-level design; and control plus fanout electronics for the orchestration of the entire DAQ and final events readout. Figure 1 contains a block diagram of the DAQ Architecture for the K0TO detector. The front-end electronics is spread over seventeen (17) 6U VME Crates, and includes three distinctive board flavours: Caesium Iodide (CsI) boards, using 14-Bit, 125 MHz ADC modules, each reading out 16 of ~3000 crystals in the K0TO CsI calorimeter. Veto Detector boards, using the same custom 14-Bit, 125MHz ADC Modules, fitted with a different firmware, for the readout of ~700 channels. Beam Hole Veto boards, using custom 12-Bit, 500MHz ADC Modules, with 4 channels per module, for the readout of up to 100 channels. The Trigger electronics is designed to provide a dead timeless first level (L1) decision based on the total calorimeter energy and a second level (L2) trigger decision based on clustering and absence of signals in the veto detectors. Events passing the L2 trigger are stored in on-board memories for readout during accelerator spills. The Trigger modules are housed in 9U VME crates with customized P3 backplane. The Trigger decision is made by the MAster Clock and TRIgger Supervisor (MACTRIS) board, which generates and fans out control signals to the whole system, oversees the event readout and communicates with the Event Builder (EVB) and the accelerator. Figure 1: Block diagram of the DAQ Architecture for the KOTO detector.