Electron Holography Characterization of Shallow Junction Fabricated By Diffusion-less Process for Sub-30 nm Gate-Length MOSFETs

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Cross‐sectional electron holography was used for two‐dimensional potential mapping of source/drain extensions (SDEs) in scaled MOSFETs fabricated using state‐of‐the‐art junction formation technology. First, we show that specimen‐preparation artifacts, which have prevented detailed examinations of scaled SDEs, are significantly reduced by using low‐energy backside Ar+ milling. Next, we demonstrate that electron holography clearly reveals very shallow (10‐nm‐deep) SDE junction profiles. We also show that the experimental examinations, in conjunction with doping‐process simulations, allow examinations of how dopant distribution, such as junction depth and abruptness, affect the potential distribution in planar‐bulk MOSFETs approaching the scaling limit.