Electron Holography Characterization of Ultra Shallow Junctions in 30-nm-Gate-Length Metal–Oxide–Semiconductor Field-Effect Transistors

Abstract

We demonstrate that electron holography can be used to map the electrostatic potential in source–drain extensions (SDEs) of 30-nm-gate-length metal–oxide–semiconductor field-effect transistors (MOSFETs). To reduce specimen-preparation artifacts, which have prevented the electron holography of advanced MOSFETs, we prepared specimens using low-energy backside Ar ion milling. Our analysis revealed the potential distributions in SDEs formed by a co-implantation technique and those formed by a conventional BF2 implantation technique and showed that the potential change at the p–n junctions is more abrupt in the former. We also show that our electron holography results clearly describe the roll-off characteristics of the MOSFETs.