Electromigration failures under bidirectional current stress

Abstract

Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed-DC (local VCC and VSS lines) and bidirectional AC current (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. Failure mechanisms of different metallization systems (Al-Si, Al-Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under AC current stress in a wide frequency range (from mHz to 500 MHz) has been study in this paper. Based on these experimental results, a damage healing model is developed, and electromigration design rules are proposed. It shows that in the circuit operating frequency range, the “design-rule current” is the time-avera...