Electromigration under time-varying current stress

Abstract

Interconnect failure as a result of electromigration is one of the major IC reliability concerns. The continuing trend of scaling-down feature sizes has exacerbated this problem. Electromigration failure under DC stress has been studied for more than 30 years, and the methodologies for accelerated DC testing and design rules have been well established in the IC industry. However, the electromigration behavior and design rules under time-varying current stress are still unclear. In CMOS circuits, as many interconnects carry pulsed DC (local V CC and V SS lines) and bidirectional AC (clock and signal lines), it is essential to assess the reliability of metallization systems under these conditions. The goal of this review is to clarify the failure mechanisms by examining different metallization systems (Al–Si, Al–Cu, Cu, TiN/Al-alloy/TiN, etc.) and different metallization structures (via, plug and interconnect) under pulsed DC and AC stress in a wide frequency range (from millihertz to 500 MHz). Based on these experimental results, a defect relaxation model under pulsed DC stress and a damage healing model under AC stress are developed, and electromigration design rules under these circumstances are proposed. This review shows that in the circuit operating frequency range, the “design rule current” is the time-average current for both pulsed DC and AC cases. The pure AC component of the current only contributes to self-heating, while the average (DC component) current contributes to electromigration. To ensure longer thermal migration lifetime under high frequency AC stress, an additional design rule is proposed to limit the temperature rise due to self-joule heating.