Abstract
A simple electromechanical diode nonvolatile memory (NVM) cell design was recently proposed and demonstrated to be well suited for implementation in a cross-point memory array architecture. In this paper, a scaling methodology for this new NVM technology is developed with the aid of a calibrated analytical model. A nanoelectromechanical NVM cell (with 20-nm minimum feature size) is projected to operate with voltages below 2 V and sub-1-ns programming time.
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