Abstract
During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, Ion/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.
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