Electrical performance of top-gate amorphous silicon thin-film transistors

Abstract

In this paper, we have studied the electrical performance of a top-gate staggered hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT). This type of TFT has an I/sub ON//I/sub OFF/ ratio of about 10/sup 6/ for the drain-source voltage Vds=10 V. Its threshold voltage V/sub T/ is about 2V. Using the current-voltage characteristics of TFTs with different channel lengths, we extract the intrinsic field-effect mobility of about 0.23 cm/sup //Vsec. We also find that the specific contact resistance of this top-gate TFT is about 17 /spl Omega/-cm/sup 2/, which is still too high for the applications in the TFT liquid crystal display (TFT-LCD). Channel conduction activation energy, which is deduced from the TFT I-V characteristics at different temperature, is about 0.18 eV when the transistor is in ON-state. For the bottom-gate TFT, the ON-state activation energy is about 0.12 eV. The estimated interface state density, obtained by field-effect (FE) method, is about 10/sup 12/ cm/sup -2/ eV/sup -1/, which is about one order of magnitude higher than that obtained for the bottom-gate TFT. We have found that bias-temperature-stress (BTS) induced shift in threshold voltage (/spl Delta/V/sub T/) follows closely the stretched-exponential stress time dependence. A stretched-exponential exponent /spl beta/ extracted at 80/spl deg/C for the top-gate TFT is slightly larger than the one for the bottom-gate TFT. The subthreshold behavior of the top-gate TFT is observed to degrade significantly under large positive bias stress condition, which indicates the trapping of negative charges or/and creation of negative defect states.