Abstract
Liquid phase deposited silicon dioxide (LPD-SiO/sub 2/) is applied to crystalline Si metal-oxide-semiconductor (MOS) capacitor as the gate insulator. It is demonstrated that slow states exist at the Si/SiO/sub 2/ interface which cause hysteresis in the capacitance-voltage (C-V) characteristics. These slow states can be removed effectively by post-metallization-anneal. By means of C-V measurement and infrared absorption spectroscopy, it is concluded that the slow states are originated from the residual water or hydroxyl molecules in LPD-SiO/sub 2/. The LPD-SiO/sub 2/ is also applied to fabricate amorphous silicon (a-Si:H) thin film transistor (TFT) based on a new self-aligned process. The performance of this device is comparable to those of thin film transistors employed other kinds of SiO/sub 2/, i.e., thermal, plasma, vacuum evaporation, etc., as the gate insulator. The bias-stress measurement shows that the threshold voltage shift is dominated by charge trapping in the gate insulator.
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