Abstract
We have investigated electrical resistivities of high-purity ultrafine-grained Cu containing different concentrations of nanoscale growth twins, but having identical grain size. The samples were synthesized by pulsed electrodeposition, wherein the density of twins was varied systematically by adjusting the processing parameters. The electrical resistivity of the Cu specimen with a twin spacing of 15nm at room temperature (RT) is 1.75μΩcm (the conductivity is about 97% IACS), which is comparable to that of coarse-grained (CG) pure Cu specimen. A reduction in twin density for the same grain size (with twin lamellar spacings of 35 and 90nm, respectively) results in an increment in electrical resistivity from 1.75to2.12μΩcm. However, the temperature coefficient of resistivity at RT for these Cu specimens is insensitive to the twin spacing and shows a consistent value of ∼3.78×10−3∕K, which is slightly smaller than that of CG Cu (3.98×10−3∕K). The increased electrical resistivities of the Cu samples were ascribed dominantly to the intrinsic grain boundary (GB) scattering, while the GB defects and GB energy would decrease with increasing twin density. Transmission electron microscope observations revealed the GB configuration difference from the Cu samples with various twin densities. Plastic deformation would induce an apparent increase in the resistivity. The higher of the twin density, the higher increment of RT resistivity was detected in the Cu specimens subjected to 40% rolling strain. Both the deviated twin boundaries and strained GBs may give rise to an increase in the resistivity.
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