Electrical investigation of the Au/n+–GaAs and Au/n-porous GaAs structures

Abstract

The electrical properties of Au/n+–GaAs and Au/n-porous GaAs metal–semiconductor structures were investigated using room temperature current–voltage I(V) and capacitance–voltage C(V) measurements. The electrical parameters of these structures such as ideality factor, barrier height potential, series resistance have been calculated. The obtained parameters of Au/n-porous GaAs structure were discussed and compared to those of Au/n+–GaAs structure. The series resistances and ideality factors of the two structures were seen to have approximately the same values. Furthermore, the shunt resistance and the barrier height potential values for the Au/n-porous GaAs structure were found to be different than the ones of Au/n+–GaAs structure. Furthermore the two structures showed a non-ideal I(V) behavior with an ideality factor greater than unity. Such non ideal behavior was suggested to be due to the existence of high density of trap and the forward I(V) characteristics which were governed by space charge limited conductivity, characterized by single and exponential trapping levels in both structures (SCLC). A model based upon TFE tunneling of carriers at reverse current was used to explain the non-saturation of reverse current of the structures. The high frequency C(V) characteristics of the structure reveal the presence of an anomalous behavior at the forward bias. Though the capacitance reaches a peak, it remarkably decreases with an increasing bias voltage suggested by the presence of interface states. Furthermore, the energy distribution of interface density in the structures was determined by the forward bias C(V) measurement as well as using ideality factor and barrier height potential values obtained from forward bias I(V) and reverse bias C−2(V) characteristics, respectively. An estimated energy band diagram for the Au/n+–GaAs and Au/n-porous GaAs structures are presented.