Electrical Instability in Pentacene Transistors with Mylar and PMMA/Mylar Gate Dielectrics Transferred by Lamination Process

Abstract

This study deals with electrical instability under bias stress in pentacene-based transistors with gate dielectrics deposited by a lamination process. Mylar film is laminated onto a polyethylene terephthalate (PET) substrate, on which aluminum (Al) gate is deposited, followed by evaporation of organic semiconductor and gold (Au) source/drain contacts in bottom gate top contact configuration (Device 1). In order to compare the influence of the semiconductor/dielectric interface, a second organic transistor (Device 2) which is different from the Device 1 by the deposition of an intermediate layer of polymethyl methacrylate (PMMA) onto the laminated Mylar dielectric and before evaporating pentacene layer is fabricated. The critical device parameters such as threshold voltage (VT), subthreshold slope (S), mobility (μ), onset voltage (Von) and Ion/Ioff ratio have been studied. The results showed that the recorded hysteresis depend on the pentacene morphology. Moreover, after bias stress application, the electrical parameters are highly modified for both devices according to the regimes in which the transistors are operating. In ON state regime, Device 1 showed a pronounced threshold voltage shift associated to charge trapping, while keeping the μ, Ioff current and S minimally affected. Regardless of whether Device 2 exhibited better electrical performances and stability in ON state, we observed a bias stress-induced increase of depletion current and subthreshold slope in subthreshold region, a sign of defect creation. Both devices showed onset voltage shift in opposite direction.