Abstract

Partial reconfiguration (PR) of a reconfigurable fabric is typically performed at run-time at the level of a frame (the smallest independently reconfigurable unit). Large frames often cause many elements to be reconfigured unnecessarily, causing the partial reconfiguration time to increase. While reconfiguring a large number of small frames, reduces the number of configuration bits used, it is also a problem on conventionalarchitectures because the frames to be reconfigured are selected, one by one, using a 1-hot decoder. Thus, key to using small frames and reducing partial reconfiguration time is hardware that can efficiently generate many subsets of frames. Specifically, if Zn = {0,1,..., n-1} is the set of all frames, then the hardware must efficiently generate a set J = Si : Si ⊂ Zn} subset of Zn of subsets of frames. It has been shown that a MU-Decoder can generate the above set S efficiently, provided its elements satisfy the property of total-ordering.In this paper we show the condition for efficient generation of S can be made much less restrictive than isomorphic total ordering and the number of subsets produced increased, even without an increase in the order of hardware resources (gates and delay) of the MU-Decoder. These results can also be used as a basis for producing subsets that are not necessarily in total-order, lending further utility to the MU-decoder.

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