An Architecture for Configuring an Effcient Scan Path for a Subset of Elements

Abstract

Many FPGAs support partial reconfiguration, where the states of a subset of configurable elements is (potentially) altered. However, the configuration bits often enter the chip through a small number of pins. Thus, the time needed to partially reconfigure an FPGA depends, to a large extent, on the number of configuration bits to be input into the chip. This is a key consideration, particularly where partial reconfiguration is performed during the computation. Therefore, it is important that the size of a frame (an atomic configuration unit) be small and the configuration be focused on the bits that truly need to be altered. Suppose C denotes the set of elements that need to be configured during a partial reconfiguration phase, here C is a (small) subset of k frames from a much larger set S of n frames. In this paper we present a method to configure the k elements of C by setting up a configuration path that strings its way through only those frames that require reconfiguration, the configuration bit stream can be now shifted in through this path. Our method also automatically selects (in hardware) a suitable clock speed that can be used to input these configuration bits. If the elements of C show spatial locality, then the configuration time could be made largely independent of n.