Efficient non-blocking optical router for 3D optical network-on-chip

Abstract

The number of cores in the multiprocessor system on the chip is growing exponentially because of the computational requirements of the applications. Efficient communication between processors on a chip intensely impacts the performance of the on-chip multiprocessor system in terms of power, speed, and space requirements. To tackle such complex integrated interconnect technology systems, three-dimensional (3D) Optical Network-on-Chip (ONoC) is a promising solution. As the optical router is a core of 3D ONoC, it needs the optimized router design in terms of the number of components used, insertion loss, power consumption, and other parameters. This paper proposes a novel design of a 6 × 6 intra-layer non-blocking optical router and an inter-layer (vertical) optical router using a micro-ring resonator (MRR). The performance analysis is carried out using the Phoenix simulator. The proposed 6 × 6 optical router has the lowest number of waveguide crossings and waveguide bendings than existing non-blocking optical routers of 3D ONoC. Furthermore proposed inter-layer optical router has reduced the number of waveguide crossings. The ONoC with X-Mesh topology using our design outperforms in terms of insertion loss and signal to noise ratio over benchmarks.