Optimized 6x6 Optical Router for Three Dimensional Optical Networks-on-Chip

Abstract

The interconnection network is very influential in Multiprocessor system-on-chip (MPSoC) performance. Due to low power efficiency and high latency, conventional interconnects are replaced by electrical networks on-chip (ENoC). However, ENoCs cannot gratify the bandwidth, latency and loss requirements within the available power budget of optical integrated circuits. The reasons being restricted bandwidth, extended delay, and reasonably high power consumption. So, ENoC are being replaced by optical networks-on-chip (ONoC). ONoC has emerged as a promising substitute to provide greater bandwidth, low latency and low power ingestion in MPSoCs. Number of cores required on-chip is increasing which leads to demand of multilayer multi-core processors. Three dimensional (3D) ONoC has become essential for such multilayer multi-core processors. For 3D ONoC, in this paper we have proposed 6x6 non-blocking optical router using micro-ring resonator (MRR) with less number of waveguide crossings and waveguide bendings. Phoenix software is used to simulate proposed optical router. Insertion loss of proposed optical router is lowest among existing non-blocking optical routers of 3D ONoC.