Efficient memory management scheme for pipelined shared-memory FFT processors

Abstract

This paper presents an efficient memory management scheme for pipelined shared-memory architectures of the fast Fourier transform (FFT). A multi-path delay commutator (MDC) with a data relocation scheme is developed to merge multiple banks for lowering the area requirement and power dissipation of pipelined shared-memory FFT architectures. Moreover, a generalized memory addressing algorithm that can support mixed-radix MDC architectures is also proposed. The presented architecture outperforms conventional pipelined shared-memory FFT designs, which employ multi-bank memory structures, in terms of the area requirement and power consumption.