Abstract
An efficient design of combined radix-2 Single path Delay Feedback (SDF)-Single path Delay Commutator (SDC)-Decimation In Frequency (DIF) algorithm is proposed in this paper which can be used in Orthogonal Frequency Division Multiplexing (OFDM) with Multiple Input Multiple Output (MIMO) applications. The MIMO-OFDM communication system has tremendous and swift growth in various applications used over last decade, especially wireless and digital communication where adaptability, reconfigurability, less chip size, hardware improvements, and lower power consumption are mandatory requirements during communication. The main aim of this structure is to improve the performance of combined Fast Fourier Transform (FFT) for the MIMO-OFDM system and also to reduce the complexity of the hardware.
Highlights
In recent years, Fast Fourier Transform (FFT) has played a significant role in Multiple Input Multiple Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) communication system applications
FFT has played a significant role in MIMO-OFDM communication system applications
Proposed combined Single path Delay Feedback (SDF)-Single path Delay Commutator (SDC) architecture is used to perform a single stage of single-path delay feedback, and all other stages are used in SDC
Summary
FFT has played a significant role in MIMO-OFDM communication system applications. The FFT calculation must be high-throughput and low-latency in all these systems. High-performance FFT circuit design is an efficient solution to the above-mentioned issues. MIMO-OFDM techniques face a lot of challenges in the present world. For improving their architecture investigation, different FFT model has been designed by large endeavours. FFT brings cost efficiency, flexibility, and power to drive and establish long distance communications. In this paper, pipelined combined radix DIF architecture is designed. The combined DIF FFT architecture is used to increase the throughput and speed of the processing element. To improve the performance of architecture, combined FFT structure is proposed. To reduce the power, area and latency in terms of Very Large Scale Integration (VLSI) concerns
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