Efficacy of Transistor Stacking on Flip-Flop SEU Performance at 22-nm FDSOI Node

Abstract

Fully depleted silicon-on-insulator (FDSOI) technology nodes offer better single-event performance compared with comparable bulk technologies. However, upsets are still possible at nanoscale feature sizes and additional hardening techniques need to be explored. Single-event upset (SEU) performance of multiple flip-flop designs using the stacked-transistor hardening technique at a 22-nm FDSOI technology node is presented in this paper. Irradiation results show significant reductions in SEU cross-sections for stacked-transistor-based hardened designs compared to a conventional design. Alpha particle exposures showed zero upsets for all D-Flip-Flop (DFF) designs tested. When exposed to heavy-ions, the stacked-transistor DFF design showed a 17X improvement over a conventional DFF design at an LET value of 47 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. The stacked-transistor design with the charge-cancelling technique showed upsets when particle LET exceeded 93.8 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg and at a high angle of incidence. The stacked-transistor design with the interleaving technique showed zero upsets for all test conditions.