Abstract
Aluminum and its alloys are the major materials used for interconnects in integrated circuits. However, their resistivities are not low enough to operate ultra-large-scale integration (ULSI) circuits at ultrahigh speeds because the parasitic capacitances of interconnects increase according to the scaling down of their physical dimensions. Furthermore, aluminum and its alloys are liable to show poor reliability against failures caused by elecromigration and stress migration. Copper (Cu) is an attractive alternative to these materials and has been investigated for applications in interconnect formation [1, 2]. The obvious advantage for using copper stems from its low resistivity (1.72 iUcm) leading to low R±C delays, where R and C, respectively, represent the resistance and capacitance associated with interconnect architecture, and expected higher electromigration resistance. The lower resistivity of copper will also act to prevent Joule heating that should aid in this regard, as well. However, because of the difference in the thermal expansion coef®cients (a) between the copper ®lm and the silicon substrate (aCu 17 3 10y6 8Cy1 and aSi 33 10y6 8Cy1, respectively), the larger Young's modulus than aluminum (ECu 12:98 3 10 dyn cmy2, EAl 7:06 3 10 dyn cmy2) and the large difference in thickness (h) between the ®lm and substrate (hSi=hCu 400 500), large biaxial stresses are generated in the copper ®lms during the thermal treatments required for device fabrication. Film stresses as large as 210 MPa (compressive) during heating and 400 MPa (tensile) at room temperature have been measured [3]. These large stresses may produce changes in the ®lm and interconnect morphologies that are deleterious to device manufacturing yield and ultimate circuit reliability. The large compressive stresses produce hillocks [4] on the ®lm surface that lead to interlevel short circuiting between metallization layers. Tensile stresses produce voids [5, 6] in passivated ®lm that locally reduce the ®lm cross-section and currentcarrying capability of the interconnects. Mechanical, physical and chemical properties of thin ®lms are affected by microstructural attributes such as grain size, grain size distribution, defect density and texture. Film texture is of particular interest owing to the anisotropic property variations observed in copper. For example, the texture of electroless copper ®lm has been shown to affect the resulting oxidation behavior [7]. The correlation of roomtemperature stress with texture and the subsequent in uence on ®lm resistivity has also been noted [8]. Ohmi et al. found that (1 0 0) and (1 1 1) preferred orientation Cu ®lms were grown on Si substrates by a low kinetic energy particle process, and (1 1 1)oriented ®lms thus created on SiO2 were metastable and easily transformed by thermal annealing into completely (1 0 0)-oriented ®lms with large grains of about 100 im [9]. A recent paper discussed the observed texture responses of copper thin ®lms deposited by a variety of techniques [10], in general, (1 0 0)-, (1 1 0)-, (1 1 1)and (5 1 1)-oriented ®lms dominated the response. From surface energy considerations, the close-packed (1 1 1)-oriented grains should be favored. An understanding of these preferred abnormal orientation grain growths has remained elusive [11]. The purpose of this letter is to explain the often extensive fraction of (1 0 0), (1 1 0), (1 1 1) and (5 1 1) texture component during thermal annealing by considering the effect of grain crystallographic orientation, with respect to the direction of the applied biaxial strains, on ®lm stresses. We assume that the polycrystalline ®lms with a facecentered cubic (f.c.c.) structure (for example, Cu or Al) are deposited on rigid silicon substrates and that the grain structure is columnar in the ®lm, that is, the grain height is equal to the ®lm thickness. The ®lm thermal stress (oe) at temperature (T ) induced by thermal expansion mismatch is given by
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