Effects of Etching Variation on Ge/Si Channel Formation and Resulted Device Behavior

Abstract

As CMOS technology scales down to 22nm, traditional planar transistor architectures have reached a fundamental limit for the required short channel control necessary to continue scaling. For good channel control, 3D transistors such as FinFET, tri-gates, and gate-all-around (GAA) FETs are the preferred devices for the sub-20nm CMOS technologies and beyond. Beside the Si channel, Ge-based systems remain the most interesting for emergent device integration. The Ge epichannel directly on Si can be a low-cost solution for the future Si technology nodes, beside the bulk Ge and the SiGe graded buffer technologies. Ge integrated with Si is not straightforward since the 4% lattice mismatch between Ge and Si generates the misfit and threading dislocations. The misfits of the bottom Ge can be removal by anisotropic etching with sensitivity to the defects. The nearly defect-free Ge channel can be formed for GAA transistors. This work reviews the two major remaining challenges that Ge/Si based devices must overcome if they are to replace Si as the channel material, namely, heterogeneous integration of Ge on Si substrates, and developing a suitable gate stack. Next, adjusting the HBr/Cl2 plasma ratio and bias power, different fin-like field-effect transistor structures can be fabricated. This process allowed for better gate control than conventional rectangular fins due to the GAA Ge/Si Channel fabricated using the process. Etching decided that Ge is compared to Si materials in terms of p-channel device performance to review how it became the first choice for PMOS devices. Different Ge/Si device architectures, including surface channel and device behavior configurations, are reviewed. Finally, state-of-the-art Ge/Si device results and future prospects are also discussed.