Effects of different drop test conditions on board-level reliability of chip-scale packages

Abstract

In this study, reliability performances of board-level chip-scale packages subjected to four JEDEC drop test conditions: A (500 G; 1.0 ms), B (1500 G; 0.5 ms), F (900 G; 0.7 ms), and H (2900 G; 0.3 ms) were evaluated experimentally and numerically. For each of the test conditions, over 80% of the failed solder joints fractured on the package side. Among the four test conditions, condition A led to the best drop resistance while condition H the worst. Though drop resistances resulted from conditions B and F were close to each other, the former contained a greater portion of failure identified as test board pad peeling. Numerical solutions of interfacial stresses, obtained by the transient finite element analysis, provided a supporting basis for the crack propagation observed from the experiments, for which the crack initiated from the inner corner of the solder joint on the package side and propagated outwards. The strain rates were found to be within 10 2 s −1 for the four drop test conditions. Using computed maximum interfacial normal and shear stresses, a fatigue reliability model that predicts the drop counts for different drop test conditions was established.