Abstract
Board level drop impact tests to evaluate electronic package mounts on printed circuit board (PCB) solder joint reliability is critical, especially for handheld and mobile consumer products. Standard drop tests refer the JEDEC specification (JESD22-B111) for PCB design and testing conditions. There are several studies about the board level drop reliability of electronic products to focus on the solder joint failure mechanism (e.g., the crack location and characteristics) under the JEDEC standard. However, the literatures lack a study of the correlation of the PCB dynamic strain and solder joint stress during the board level drop impact and real product system level shock test. In this work, a 15x15 mm2 Quad Flat No Leads (QFN) package which is Wi-Fi module function used in industry scanner product was chosen to measure the peak acceleration and PCB strain under 1.2 meter height system level free drop. The maximum PCB strain would be used to correlate with standard board level drop tests to measure and calculate acceleration response. From the result, it shows that at similar PCB strain response the system level free drop tests peak acceleration is about 2900G and the board level drop tests peak acceleration is about 325G.Besides, the 3D transient numerical model based on the support excitation scheme was also performed to obtain thorough understanding of structural responses of the test vehicle and reliability of its solder joints under different test conditions. This model would be used to compute solder joint maximum interfacial normal and shear stresses. A fatigue reliability model that predicts the drop counts for different drop test conditions of JEDEC drop test condition: B (1500 G; 0.5 ms) and system-like condition: (325 G; 0.576 ms) was established. This study provides an accurate and reliable way to understand the correlation between system level and board level drop tests solder joint stress and to help to achieve service life improvements in early development stage.
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