Effects of Base Oxide Thickness and Silicon Composition on Charge Trapping in HfSiO/SiO2 High-k Gate Stacks

Abstract

This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf–OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.