Abstract
AbstractThis paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.
Published Version
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