Effect of wafer thickness on sheet resistance during spike annealing

Abstract

Temperature control requirements for Rapid Thermal Anneal (RTA) process steps, notably the source/drain activation anneal, have reached the limits of process capability at the 65 nm node. Device requirements dictate the tools be matched to better than 2°C and peak-temperature controlled to better than 1°C at ramp-up rates between 75°C/s and 230°C/s. It is important to understand all sources of variation in the time-temperature profile and the effects of this variation on measured parameters such as sheet resistance (Rs) on both monitor and product wafers. This work examines the effect of wafer thickness on the time-temperature behavior during the RTA process and its subsequent effect on Rs. It is shown that thicker wafers lead to a lower Rs. Nominal wafer thickness is 750 μm, but a variation in thickness of 10 μm results in an Rs shift of 0.5 ohms/square, the equivalent to a peak-temperature change of 0.63°C. This behavior is shown to have a significant effect on both monitor and product wafers. A study of 100 Hz data from the RTA chamber shows that this effect is likely due to two factors: (1) Thicker wafers reach a higher peak temperature, and (2) after reaching peak temperature, thicker wafers cool more slowly. Peak temperature reached is seen to change by 0.34°C per 10 μm of thickness change. The cooling rate changes by approximately 1°C/s per 10 μm of thickness change. Together, higher peak temperature and lower cooling rate result in a higher thermal budget, greater activation, and lower Rs for thicker wafers.