Effect of UV/VUV Enhanced RTP on Process Variation and Device Performance of Metal Gate/High-<tex>$kappa$</tex>Gate Stacks for the Sub-90-nm CMOS Regime

Abstract

We show that UV/VUV-enhanced rapid thermal processing (RTP) in combination with single-wafer processing using a single tool for the fabrication of metal gate/high-/spl kappa/ dielectric gate stacks not only improves overall device performance, but also leads to a significant reduction in process variation at the front end of the CMOS process flow for the sub-90-nm technology node. The gate stacks were fabricated under various UV/VUV conditions. Gate stacks processed under UV/VUV radiation during all processing steps displayed low leakage currents of the order of 10/sup -11/ A/cm/sup 2/. It is shown that the Al-Al/sub 2/O/sub 3/-Si gate stacks processed under UV/VUV conditions also display the lowest variations both in mean leakage current and mean capacitance, as compared to devices where UV/VUV was not used for all the processing steps. Therefore, it can be see that reliance on successive corrective iterations common to automatic process control or standard design simulation can be reduced significantly. As a result, UV/VUV-enhanced RTP has the potential to reduce the effect of process variations on overall device performance, thereby making the overall process more cost effective and time efficient and therefore improving yield and device reliability.