Advantages of in-situ RTP for the fabrication of metal/high-dielectric constant gate dielectric stack for sub 90 nm CMOS technology

Abstract

In order to reduce the costs of single wafer processing and improve overall device performance by reducing contamination levels and hence defect generation during processing, in-situ processing of metal-insulator-semiconductor stacks may become a necessary CMOS processing step. In earlier work, the importance of ultra thin high-/spl kappa/ dielectric processing using rapid thermal processing (RTP) was investigated. We have now extended this approach by growing the metal gate electrode on top of the high-/spl kappa/ dielectric layer of the dielectric stack. In this paper, we present preliminary results, which show, that the leakage characteristics of metal-insulator-semiconductor (MIS) structures with ultra-thin Al/sub 2/O/sub 3/ films as high-/spl kappa/ insulators may be improved significantly via the in-situ deposition of the dielectric stack in a single chamber.