Effect of the Degree of the Gate‐Dielectric Surface Roughness on the Performance of Bottom‐Gate Organic Thin‐Film Transistors

Michael Geiger,Jens Pflaum,Jürgen Weis,Ralf Thomas Weitz,Thomas Ferschke,Hagen Klauk,Eric Reutter,Ute Zschieschang,Rachana Acharya

doi:10.1002/admi.201902145

Abstract

AbstractIn organic thin‐film transistors (TFTs) fabricated in the inverted (bottom‐gate) device structure, the surface roughness of the gate dielectric onto which the organic‐semiconductor layer is deposited is expected to have a significant effect on the TFT characteristics. To quantitatively evaluate this effect, a method to tune the surface roughness of a gate dielectric consisting of a thin layer of aluminum oxide and an alkylphosphonic acid self‐assembled monolayer over a wide range by controlling a single process parameter, namely the substrate temperature during the deposition of the aluminum gate electrodes, is developed. All other process parameters remain constant in the experiments, so that any differences observed in the TFT performance can be confidently ascribed to effects related to the difference in the gate‐dielectric surface roughness. It is found that an increase in surface roughness leads to a significant decrease in the effective charge‐carrier mobility and an increase in the subthreshold swing. It is shown that a larger gate‐dielectric surface roughness leads to a larger density of grain boundaries in the semiconductor layer, which in turn produces a larger density of localized trap states in the semiconductor.

Highlights

In organic thin-film transistors (TFTs) fabricated in the inverted device structure, the surface roughness of the gate dielectric onto which the organic-semiconductor layer is deposited is expected to have a significant effect on the TFT characteristics
The surface of the aluminum was oxidized by brief exposure to an oxygen plasma, and the resulting aluminum oxide layer (AlOX) was covered with an alkylphosphonic acid selfassembled monolayer (SAM)
The X-ray diffraction (XRD) analysis confirms independently that the surface roughness of the gate dielectric does not have a significant impact on the internal morphology of the DNTT grains, which suggests that the TFT characteristics are determined exclusively by the density of grain boundaries along the lateral transport channels within the DNTT layers

Summary

Introduction

In organic thin-film transistors (TFTs) fabricated in the inverted (bottom-gate) device structure, the surface roughness of the gate dielectric onto which the organic-semiconductor layer is deposited is expected to have a significant effect on the TFT characteristics. To quantitatively evaluate this effect, a method to tune the surface roughness of a gate dielectric consisting of a thin. All TFTs were fabricated using the same materials, the same layer thicknesses, and the same process conditions, with one exception, namely the substrate temperature during the deposition of the aluminum gate electrodes (in order to analyze the impact of the surface roughness) or the substrate temperature during the deposition of the organic semicon-. By varying the substrate temperature during the DNTT deposition we can control the density of grain boundaries in the DNTT layer independent of the gatedielectric surface roughness

Gate-Dielectric Surface Roughness

Electrical TFT Characteristics and Trap-State Density

Organic-Semiconductor Morphology

Conclusion

Experimental Section

Conflict of Interest