Effect of Si cap layer on parasitic channel operation in Si/SiGe metal–oxide–semiconductor structures

Abstract

We investigate the effects of silicon cap layer thinning on channel carrier confinement in silicon/strained silicon-germanium (Si/SiGe) metal–oxide–semiconductor (MOS) structures. The silicon cap thickness is shown to have a critical influence on the induced parasitic channel in the silicon cap, which lowers the transconductance value of the buried SiGe channel in hole carrier channel p metal–oxide–semiconductor field-effect transistor devices. This can have serious consequences on future implementation of SiGe ultrashort channel devices where gate induced parasitic channel and short channel effects can be pronounced. An exact methodology is devised for consumption of silicon cap layer using a modified Radio Corporation of America surface standard clean self-terminating chemical oxide and rapid thermal oxide growth. This provides (i) precise control over the silicon cap and thermal oxide thickness and (ii) a limit on the amount of thermal budget induced strain relaxation in the buried SiGe layer. The threshold voltages for inversion of carriers at the SiO2/Si and the Si/SiGe interfaces are extracted as functions of Si cap thickness. A transition from dual to single channel operation in MOS devices at room temperature on thinning the silicon cap layer is observed with capacitance–voltage measurements. Cross-section transmission electron microscopy and secondary ion mass spectroscopy techniques are used to calibrate and support the developed methodology for Si cap layer etch control and the effect of Ge species at the oxide–heterostructure interface. There is a high fixed charge density, which indicates Ge pileup at the SiO2/SiGe interface. Our analysis suggests that about 1 nm of silicon cap retention is necessary to minimize the gate induced parasitic channel and to decouple the oxide interface trap influence on the channel carriers in the SiGe.