Abnormal hump in low temperature in SiGe devices with silicon capping insertion layer

Abstract

This study compares the capacitance–voltage (C–V) characteristics in silicon–germanium (SiGe) metal-oxide-semiconductor capacitances with and without a silicon oxide capping layer. The SiGe channel with the silicon oxide capping layer exhibits an improved C–V property at room temperature but has an abnormal shift and depression at low temperature (77 K). We determined that the threshold voltage shift was induced by the Fermi-level when ambient temperature was changed. The additional silicon capping layer was responsible for introducing defects resulting in depression and hump in the C–V measurements. Such a phenomenon is mainly caused by the different distribution of defects, which was established by modifying the alternating current pulse amplitude during the C–V measurement.