Abstract
In this paper, we study the inference accuracy of Resistive Random Access Memory (ReRAM) based neuromorphic circuit under various array faults using fully analog SPICE simulations. The ReRAM Verilog-A model is calibrated to the experiment and a 45nm realistic Process Design Kit (PDK) is used. A handwritten dataset is used for the demonstration with a neural network containing 3 hidden layers. The faults studied include the random variations of ReRAM gap size due to gap size drifting and the “stuck-off” faults with various spatial shapes in the ReRAM arrays. We also study how the faulty array location in the neural network affects circuit fault tolerance. Finally, we propose fault-aware processing and layout guidelines for extending the lifetime of ReRAM neuromorphic circuits for Internet-of-Things (IoT) applications.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
