Effect of Guard Ring Design and Properties of Inter-Layer Dielectric Film on Chip Reliability

Abstract

One of the common reliability problems in semiconductor industry is delamination of dielectric films used in the integrated circuit manufacturing process. Although these films have demonstrated good reliability performance in wafer form, once placed in different packages and undergo stress testing (e.g. pressure cooker test) they tend to crack and delaminate and lead to eventual reliability failure of the chip. The die guard ring can impact propagation of cracks that are initiated at the edge of the die into the active circuitry of the die. We designed several guard ring structures and performed finite element analysis to compare the potential of crack propagation for different guard ring designs. It is found that some features of the design do not affect stress intensity factor KI (potential of crack propagation). For long crack (3.75 um), structure A may reduce KI. But, structure B will increase KI. From fracture mechanics point of view, structure A may stop crack propagation toward die center. However, with structure B, the crack may still penetrate into the die. For short crack (1.25 um), effect of guard ring structure design is negligible. We have made experimental wafers using our wafer manufacturing processes to create structure A and B around the dice. Some wafers were made with film AA as interlayer dielectric and some with film BB as interlayer dielectric. SEM inspections validate our FEM models that structure A captures more cracks at the edge of the die and prevents its propagation into the die while structure B is less effective. We have shown that even with incorporation of structure B guard ring, film BB looses adhesion to other layers and delaminates upon exposure to humidity in pressure cooker test while film AA never delaminates.