Effect of Gate–Drain Spacing for In0.52Al0.48As/In0.53Ga0.47As High Electron Mobility Transistors Studied by Monte Carlo Simulations

Abstract

We performed two-dimensional Monte Carlo (MC) simulations of 60-nm-gate InP-based lattice-matched In0.52Al0.48As/In0.53Ga0.47As high electron mobility transistors (HEMTs) to clarify the effect of the gate–drain spacing Lgd on device performance. The calculated maximum transconductance gm and cutoff frequency fT increase with decreasing Lgd down to 50 nm, which agrees with experimental values. To explain the increase in gm and fT, we obtained electron velocity profiles in the InGaAs channel layer. Electron velocity overshoot under the gate is enhanced with decreasing Lgd. The resulting average electron velocity under the gate increases with decreasing Lgd. The enhancement of the electron velocity overshoot can be explained by using potential profiles in the HEMT. Potential profile under the gate in the InGaAs channel becomes steeper with decreasing Lgd.