Abstract
In this paper, the effect of fringe induced barrier lowering (FIBL) in-conjunction with channel parameters that includes channel thickness (TSi), channel length (Lg) and lateral straggle (σL) on analog and RF performance of FinFET, have been studied using TCAD mixed-mode Sentaurus device simulator. We focused on the variation in analog (intrinsic dc gain) and RF (cut-off frequency) figure of merit (FOM) of high-K gate dielectric based FinFET with respect to channel parameters. It is observed that the variation in intrinsic dc gain (ΔAV) aggravates with TSi scaling. We also observe a mixed response to the ΔAV with respect to variation in Lg and σL, where ΔAV follows an inverse parabolic behavior peaking at an intermediate value of Lg and σL. Variation in cut-off frequency (ΔfT) on the other hand, is negligible (slightly increases with TSi and decreases with Lg and σL). These properties of channel parameters can be handy in designing of high-K gate dielectric based FinFET for analog circuits.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.