Analog/RF performance analysis of channel engineered high-K gate-stack based junctionless Trigate-FinFET

Abstract

In this paper, the effect of channel parameters like channel thickness (TSi) and channel length (Lg) on the analog/RF performance of high-K gate-stack based junctionless Trigate-FinFET (JLT-FinFET) have been studied using TCAD mixed-mode Sentaurus device simulator. It is observed that use of high-K gate dielectric deteriorates the analog/RF performance of the gate-stack based JLT-FinFET. The variation of change in analog/RF FOMs (ΔFOM = FOMK=3.9 - FOMK=40) with respect to channel parameters have been focused throughout this study. It is observed that the deterioration in intrinsic dc gain (ΔAV = (AV(K=3.9) - AV(K=40))) with high-K gate dielectrics aggravates with scaling down of TSi (from 2.31 dB at TSi = 12 nm to 5.2 dB at TSi = 6 nm) but increases marginally with scaling down of Lg (ΔAV = 7.6 dB at Lg = 30 nm and ΔAV = 8.7 dB at Lg = 15 nm). However, the deterioration in maximum oscillation frequency (ΔfMAX) and cut-off frequency (ΔfT) are almost negligible. Moreover, it is also observed that the deterioration in analog/RF FOMs due to high-K gate dielectrics can be reduced by upscaling of interfacial layer thickness (TI). Consequently, higher TI value can be convenient in designing of high-K gate-stack based junctionless Trigate-FinFET at lower TSi for analog/RF applications.