Effect of Drain Bias Stress on Stability of Nanocrystalline Silicon Thin Film Transistors with Various Channel Lengths

Abstract

We report the electrical stability of bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) with various channel lengths under drain bias stress for the first time. As the bias stress at the drain terminal increases at a fixed gate bias, the threshold voltage (VTH) shift of the nc-Si TFTs decreases significantly. Under the drain bias stress, the VTH shift decreases with channel length. The smaller VTH shift was analyzed on the basis of the concentration of the channel charge. A high drain bias reduces the carrier concentration near the drain terminal. Also, the ratio of the depleted charges to total charges increases with decreasing channel length due to the drain bias. Thus, a short-channel TFT has a smaller normalized channel charge than a long-channel TFT. A low carrier concentration induces a small number of defect states; thus the VTH shift of a short-channel TFT is smaller than that of a long-channel TFT.