Dual-mechanism modelling of instability in nanocrystalline silicon thin film transistors under prolonged gate-bias stress

Abstract

A dual-mechanism model of the threshold voltage (VT) shift is proposed for the plasma deposited hydrogenated nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs) stressed under relatively high gate-bias for ∼ 106 s. ΔVT versus stress time experimental behavior is modelled by accurate fitting of the combination of stretched exponential and logarithmic dependences. Without such superposition as it is commonly done in other works, i.e. by using any single dependence only, no successful fit was obtained for the VT shift data at hand. While the stretched exponential behavior is found to be dominant at short stress times, the logarithmic behavior dominates at long stress times. These mathematically distinct behaviors are demonstrated to be attributed to totally distinct TFT instability mechanisms: defect state creation within the nc-Si:H channel layer and charge trapping in the gate insulator. The relaxation data of the stressed TFTs under room temperature support the simultaneous presence of these mechanisms during stressing. In addition, different nanocrystalline volume fractions of the nc-Si:H channel layers of two TFT sets resulted in different ΔVT versus stress time data, which also supports the dual-mechanism instability model.