Effect of asymmetric gate–drain overlap on ambipolar behavior of double-gate TFET and its impact on HF performances

Abstract

To remove simultaneously the ambipolar conduction and enhance HF performances, we propose a promising configuration of DG-TFET with asymmetric gate–drain overlap (ASGDO DG-TFET) in which only back gate is overlapped with drain region. This proposed structure of DG-TFET removes the trade-off between ambipolarity and HF performances by taking the merit of gate–drain overlap in terms of reduction in ambipolarity and suppressing its demerit with reduced gate–drain parasitic capacitance. Using 2-D simulation, it is observed that ambipolar conduction can be suppressed to a large extent in DG-TFET with only 20 nm of back gate–drain overlap, thus not limiting the scaling of drain region compared to symmetric gate–drain overlap DG-TFET (SGDO DG-TFET). Due to the presence of enhanced depletion layer in the drain region caused by a large vertical electrical field, tunneling width at drain–channel interface is found to be maximum in the proposed device, which eventually prevents the charge carriers to tunnel. Furthermore, ASGDO improves the HF performance parameters such as cutoff frequency and gain–bandwidth product compared to SGDO due to reduction in gate–drain parasitic capacitance, and this improvement is found to be consistent while scaling down the channel length.