Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior

Abstract

The goal of this work is to overcome the major impediments of tunnel FET such as the inherent ambipolar current (I AMB) and the lower ON current (I ON). To suppress the I AMB, gate drain overlap (GDO) engineering scheme has been incorporated over the cylindrical gate all around TFET (GAA-TFET). However, to enhance the I ON, heterogate dielectrics (HD) are used in the gate oxide region. Results indicate that an appreciably reduced I AMB and significantly enhanced I ON has been obtained with the amalgamation of GDO and HD, respectively, onto GAA-TFET. Further, the effect of GDO length (L ov) has also been studied. Quantitative analysis of ambipolarity factor “α” reveals that at large L ov, “α” improves. It is found that GDO degrades the high-frequency (HF) performance such as cutoff frequency (f T) of the device, because of the enhanced parasitic capacitances. To surpass the deterioration at HF caused by GDO, the dielectric over GDO region has been altered, and it has been analyzed that by inserting a material of low-dielectric constant (k = 1) and parasitic capacitances of the device reduces, resulting into enhancement in f T. Moreover, the low-k dielectric inserted over L ov reduces the I AMB supplementary, along with enhanced f T. Suppressed I AMB and enhanced f T of GDO–HD–GAA-TFET with low-k dielectric over L ov make it adequate for application in HF and digital circuitry.