Abstract
A dual-mode dynamic/static (dynastat) divided-by-two combines the range of a static frequency divider (DC-117 GHz from simulation) and the higher toggle frequency of a dynamic divider (85–153 GHz, simulated) at a low input sensitivity of 0.2 Vpk differential (<−3 dBm into 50 Ω). The measured self-oscillation frequencies of the prototype are 79 GHz (static) and 129 GHz in dynamic mode. The 8880 μm2 dynastat implemented in 90 nm silicon germanium (SiGe)-bipolar CMOS consumes 38 mA (static) and 19 mA (in dynamic mode) from a 4.5 V supply.
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