Abstract
Abstract In this paper, we propose a low-power adaptive low-density parity check (LDPC) decoder that utilizes dynamic voltage and frequency scaling to reduce power consumption. Most existing adaptive LDPC decoders have focused only on the decoding performance based on the signal-to-noise ratio (SNR) estimation. However, significant idle power is consumed when the decoder awaits the next frame after processing a frame. In mobile communication standards such as China Mobile Multimedia Broadcasting and Digital Video Broadcasting Satellite Second Generation, adaptive coding and modulation has been adopted. Thus, it is possible to reduce the power consumption efficiently by using the SNR estimation. In this paper, we apply a customized frequency selection scheme and a variable voltage generation scheme to an adaptive LDPC decoder to reduce the dynamic power consumption. The proposed schemes result in a reduction of 44% in the energy consumption of an LDPC decoder implemented using 0.18-μm complementary metal-oxide-semiconductor technology.
Highlights
Today, the need for a reliable high transmission rate is increasing in order to offer various multimedia services with 4G mobile communication systems
The critical path of the proposed adaptive low-density parity check (LDPC) decoder is found at the minimum value finder inside the check node processing unit
The proposed decoder consists of an adaptive LDPC decoder and a dynamic voltage and frequency scaling (DVFS) controller
Summary
The need for a reliable high transmission rate is increasing in order to offer various multimedia services with 4G mobile communication systems. In [9,10], adjusting either the maximum number of iterations or the quantization level according to the estimated SNR value is proposed in order to reduce the decoding power consumption.
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