Dynamic-Pseudo-Random Test Sequence Generation Technique with Low Power Consumption

Abstract

In order to provide low power consumption LFSR seed for BIST structure，this paper proposed a seed calculation Methods of dynamic-pseudo-random test sequence, it can reseed for LFSR and cut off test sequence of the low fault coverage effectively. The seed can generation fixed length pseudo-random test sequence, the sequence reduce test time and number of test vectors mostly. Experimental results that this technique can reduce the length of vectors, shorten test time and low power consumption based on without reduce the fault coverage