Abstract
A dynamic model of a SMT (surface mount technology) type 1206 chip capacitor is developed. The model is used to determine the effects of pad geometry, chip metallization and dimensions, amount of solder, and chip displacement on the ability of the chip to lift (tombstone) and to self-align itself during solder reflow. Both static and dynamic characterizations are shown. The model simulations show that the chip capacitor will begin to lift initially for some geometries, but tombstoning does not appear to be a problem. Thus, to help the self-alignment capabilities, the simulations show that system configurations with smaller pad lengths, smaller pad gaps, larger solder volume, and smaller metallization are best. These conclusions are confirmed when compared to existing recommendations based upon experimental tests. It is concluded that the model is a powerful tool that can be used to optimize these system parameters. >
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