DualFET packaging advancement through innovative source down

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For the past decades, the performance enhancement on the silicon level was the main focus of the semiconductor field since the contribution of the package to the MOSFET performance was rather small. In general, there are three key factors that determine the power semiconductor performance which is the silicon structure, wafer thinning and innovative packaging. Silicon structures still have signs of improvement but for power MOSFET technologies, the wafer thickness becomes the dominant factor for front-end assembly to get the lowest on-resistance of its vertical current functions. As such, thinner wafer thickness with thinning process is one of the technology improvements that the market is driving today. But looking at the today's technology trend, wafer thinning process and silicon structures were well developed that the performance improvement coming from the wafer assembly had already reached its limitation or saturation. As such, resistance and parasitic inductance of the package becomes the mandatory target for packaging innovation and development. Generally flip chip technology in the market utilizes the solder bump as interconnect followed by the underfill process to improve on the overall reliability and robustness of the package. The dualFET package introduced by Infineon, also known as PowerStage 5×6 has dual MOSFET in a package originally used conventional chip attach technology with standard solder dispensing. Such chip attach technology used in this MOSFET package has certain limitation to thermal performance related to heat dissipation issues on product application level. The assembly and packaging technology for this dual MOSFET package was analysed for further performance enhancement. The limitation of current packaging technology has invited an opportunity for new innovation in order to improve the thermal performance for higher efficiency in the application, an innovative package with designed-in feature for good heat dissipation which has optimized thermal path and pad design considering heat source from MOSFET chip junction temperature and innovative flip chip technology developed to enable the Source of MOSFET chip contacts directly to the leadframe Source pad with solder interconnect in between are the essential enablers. In addition, such innovative package technology not only improve the thermal performance but also enable lower parasitic for overall product and system performance enhancement. In this innovative MOSFET source down standard solder paste dispensing and flip chip technology are used for the solder die attach interconnect. This helps in maximizing the electrical and thermal contact area for the MOSFET in resulting significant reduction of thermal resistant and electrical resistant. The new packaging technology did not increase the manufacturing complexity especially the assembly processes but maintaining the same manufacturing landscape which is using the existing die attached solder as interconnect. Throughout the development of this technology, an Intellectual Property (IP) on package feature had been created which could further set Infineon as a differentiator in power packaging technology. As the result, the innovative MOSFET source down package had not only achieved significant product performance and efficiency enhancement but also creating values and business opportunities for Infineon to achieve competitive advantage.